Cite
FPGA Implementation of Bit Controller in Double-Tick Architecture.
MLA
Kobylecki, Michał, and Dariusz Kania. “FPGA Implementation of Bit Controller in Double-Tick Architecture.” AIP Conference Proceedings, vol. 1906, no. 1, Sept. 2017, pp. 1–4. EBSCOhost, https://doi.org/10.1063/1.5012400.
APA
Kobylecki, M., & Kania, D. (2017). FPGA Implementation of Bit Controller in Double-Tick Architecture. AIP Conference Proceedings, 1906(1), 1–4. https://doi.org/10.1063/1.5012400
Chicago
Kobylecki, Michał, and Dariusz Kania. 2017. “FPGA Implementation of Bit Controller in Double-Tick Architecture.” AIP Conference Proceedings 1906 (1): 1–4. doi:10.1063/1.5012400.