Cite
Optimized Design of Space Solar Array Simulator With Novel Three-Port Linear Power Composite Transistor Based on Multiple Cascaded SiC-JFETs.
MLA
Jin, Shanshan, et al. “Optimized Design of Space Solar Array Simulator With Novel Three-Port Linear Power Composite Transistor Based on Multiple Cascaded SiC-JFETs.” IEEE Transactions on Industrial Electronics, vol. 65, no. 6, June 2018, pp. 4691–701. EBSCOhost, https://doi.org/10.1109/TIE.2017.2772156.
APA
Jin, S., Zhang, D., Gu, Y., & Wang, C. (2018). Optimized Design of Space Solar Array Simulator With Novel Three-Port Linear Power Composite Transistor Based on Multiple Cascaded SiC-JFETs. IEEE Transactions on Industrial Electronics, 65(6), 4691–4701. https://doi.org/10.1109/TIE.2017.2772156
Chicago
Jin, Shanshan, Donglai Zhang, Yu Gu, and Chao Wang. 2018. “Optimized Design of Space Solar Array Simulator With Novel Three-Port Linear Power Composite Transistor Based on Multiple Cascaded SiC-JFETs.” IEEE Transactions on Industrial Electronics 65 (6): 4691–4701. doi:10.1109/TIE.2017.2772156.