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Analysis and Demonstration of an IIP3 Improvement Technique for Low-Power RF Low-Noise Amplifiers.
- Source :
-
IEEE Transactions on Circuits & Systems. Part I: Regular Papers . Mar2018, Vol. 65 Issue 3, p859-869. 11p. - Publication Year :
- 2018
-
Abstract
- This paper describes a linearization method to enhance the third-order distortion performance of a subthreshold common-source cascode low-noise amplifier (LNA) without extra power consumption by using passive components. An inductor between the gate of the cascode transistor and the power supply in combination with a digitally programmable capacitor between the gate and the drain of the cascode transistor enable to improve the third-order intermodulation intercept point (IIP3) of a subthreshold LNA. The theoretical mechanisms that underlie the linearity improvement are analyzed comprehensively under the consideration of the LNA’s input stage, cascode stage, reverse isolation, and stability. A 1.8-GHz LNA was designed and fabricated using 0.11- \mu \textm CMOS technology to prove the concept. Measurement results reveal that the linearized low-power LNA has a 14.8-dB voltage gain, a 3.7-dB noise figure, and a −3.7-dBm IIP3 with a power consumption of 0.336 mW. [ABSTRACT FROM AUTHOR]
- Subjects :
- *LOW noise amplifiers
*ELECTRONIC amplifiers
*RADIO frequency
*ELECTRIC distortion
Subjects
Details
- Language :
- English
- ISSN :
- 15498328
- Volume :
- 65
- Issue :
- 3
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Circuits & Systems. Part I: Regular Papers
- Publication Type :
- Periodical
- Accession number :
- 128115053
- Full Text :
- https://doi.org/10.1109/TCSI.2017.2781369