A near-threshold 10T differential SRAM cell with high read and write margins for tri-gated FinFET technology.

In this paper, a new 10T SRAM bit-cell working in the near-threshold region with differential read and write operations is proposed. The cell structure comprises six main body transistors having connections similar to commercial 6T SRAM cell to improve write performance and has a separate read buffer on each side of cell to improve read performance. Efficacy of the proposed bit-cell is tested in 20 nm tri-gated FinFET technology with the help of HSPICE simulations in near-V T and super-V T operating regions. Performance characteristics of the proposed bit-cell are compared with other recently reported 10T and 8T differential sensing bit-cells, along with the commercial 6T cell. The proposed bit-cell achieves 6.57%, 33.33% and 51.64% higher RSNM as compared to 10T P-P-N, 8T SRAM-NEW and 6T bit-cells, respectively, in near-V T operating region. The read delay, write delay and static power consumption of the proposed bit-cell are comparable with that of 6T bit-cell in both operating regions. The overall electrical quality of SRAM circuit with the proposed bit cell is enhanced up to 8.192, 1.13 and 2.39 times compared to that of the 10T P-P-N, 8T SRAM-NEW and 6T bit-cells, respectively, in near-V T operating region. The proposed bit-cell can operate with a 38.8%, 30% and 5.54% lower V DD as compared with 6T, 8T SRAM-NEW and 10T P-P-N bit-cells, respectively, under equal read data stability conditions. Influence of process variation on bit-cell stability is studied through 10,000 Monte Carlo simulations. The study shows that the proposed bit-cell meets the required six sigma value (6σ) for all operations even at V DD =0.5 V. Variations in the bit-cell performance metrics for temperature rise from −40 °C to 100 °C are also studied. [ABSTRACT FROM AUTHOR]