Cite
High-Speed Low-Power Flash ADC Architecture Using Switched-Capacitor Positive Feedback Comparator and Parallel Single-Gate Encoder.
MLA
Abdel-Hafeez, Saleh, and Ali Shatnawi. “High-Speed Low-Power Flash ADC Architecture Using Switched-Capacitor Positive Feedback Comparator and Parallel Single-Gate Encoder.” Circuits, Systems & Signal Processing, vol. 37, no. 6, June 2018, pp. 2492–510. EBSCOhost, https://doi.org/10.1007/s00034-017-0673-8.
APA
Abdel-Hafeez, S., & Shatnawi, A. (2018). High-Speed Low-Power Flash ADC Architecture Using Switched-Capacitor Positive Feedback Comparator and Parallel Single-Gate Encoder. Circuits, Systems & Signal Processing, 37(6), 2492–2510. https://doi.org/10.1007/s00034-017-0673-8
Chicago
Abdel-Hafeez, Saleh, and Ali Shatnawi. 2018. “High-Speed Low-Power Flash ADC Architecture Using Switched-Capacitor Positive Feedback Comparator and Parallel Single-Gate Encoder.” Circuits, Systems & Signal Processing 37 (6): 2492–2510. doi:10.1007/s00034-017-0673-8.