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A novel modified GDI method-based clocked M/S-TFF for future generation microprocessor chips in nano schemes.
- Source :
-
Microprocessors & Microsystems . Jul2018, Vol. 60, p122-137. 16p. - Publication Year :
- 2018
-
Abstract
- In this work, a novel architecture is proposed for designing the clocked master-slave TFF (M/S-TFF) based on modified gate-diffusion input (m-GDI) method. By noting that we used clocked phase scheme or feedback input technique in designing the M/S-TFF circuit. The advantages of the proposed scheme can be cited as reduce the number of required transistors, lower power consumption-propagation delay product ( PDP ) in all activity factors and layout area in comparison with similar state-of-the art designs. More importantly, Monte-Carlo simulations confirm proposed topology gains substantial variation tolerance with a substantial small standard deviation and considerable lower variability percentage in metrics than other schemes in same technology. At the end, the presented static frequency divider (SFD) using proposed M/S-TFF, works at wider frequency range with 0.198 milli-Watt (mW) power dissipation at the maximum operating frequency ( f max . ) about 46 Giga-Hertz (GHz) under 0.9 Volt supply voltage. Therefore, using the proposed scheme can be improved in data storing elements, prescaler block in phase-locked loop (PLL) chips for future of generation communication networks like: fifth generation (5G) and microprocessors performance. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 01419331
- Volume :
- 60
- Database :
- Academic Search Index
- Journal :
- Microprocessors & Microsystems
- Publication Type :
- Academic Journal
- Accession number :
- 130123728
- Full Text :
- https://doi.org/10.1016/j.micpro.2018.04.010