Cite
DANoC: An Efficient Algorithm and Hardware Codesign of Deep Neural Networks on Chip.
MLA
Zhou, Xichuan, et al. “DANoC: An Efficient Algorithm and Hardware Codesign of Deep Neural Networks on Chip.” IEEE Transactions on Neural Networks & Learning Systems, vol. 29, no. 7, July 2018, pp. 3176–87. EBSCOhost, https://doi.org/10.1109/TNNLS.2017.2717442.
APA
Zhou, X., Li, S., Tang, F., Hu, S., Lin, Z., & Zhang, L. (2018). DANoC: An Efficient Algorithm and Hardware Codesign of Deep Neural Networks on Chip. IEEE Transactions on Neural Networks & Learning Systems, 29(7), 3176–3187. https://doi.org/10.1109/TNNLS.2017.2717442
Chicago
Zhou, Xichuan, Shengli Li, Fang Tang, Shengdong Hu, Zhi Lin, and Lei Zhang. 2018. “DANoC: An Efficient Algorithm and Hardware Codesign of Deep Neural Networks on Chip.” IEEE Transactions on Neural Networks & Learning Systems 29 (7): 3176–87. doi:10.1109/TNNLS.2017.2717442.