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Design of two-terminal-electrode vertical thyristor as cross-point memory cell without selector.
- Source :
-
Applied Physics Letters . 7/30/2018, Vol. 113 Issue 5, pN.PAG-N.PAG. 5p. 1 Diagram, 3 Graphs. - Publication Year :
- 2018
-
Abstract
- We proposed a two-terminal-electrode vertical thyristor and investigated its suitability as a cross-point memory cell without a selector from the viewpoints of p+- and n+-base region width and a vertically stacked doped-epitaxial-Si layer structure such as p++-emitter/n+-base/p+-base/n++-emitter or n++-emitter/p+-base/n+-base/p++-emitter. The proper p+- and n+-base-region width (i.e., 160 nm) and p++-emitter/n+-base/p+-base/n++-emitter layer structure could enable the development of a cross-point memory cell using the half bias concept by preventing misfit dislocations at the junctions between the n++-emitter and p+-base or n+-base and p++-emitter. It was also found that generation of the misfit dislocations originating from B or P atom segregation at junctions during doped-Si epitaxial-layer growth enhanced the strain at the junctions. The misfit dislocations at the junctions were produced when the strain at the junctions was greater than ∼4 × 10−4. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00036951
- Volume :
- 113
- Issue :
- 5
- Database :
- Academic Search Index
- Journal :
- Applied Physics Letters
- Publication Type :
- Academic Journal
- Accession number :
- 131069136
- Full Text :
- https://doi.org/10.1063/1.5040426