Magnifying the effective intrinsic stress of surface coating on the performance of nano-scaled Ge-based high-k/metal gate device through superficial layout designs.

Scaling of dimensions for traditional Si-based metal oxide semiconductor field-effect transistors (MOSFETs) is limited. Thus, a promising transistor material and a corresponding fabricated process should be selected to improve the electrical performance of advanced nanodevices. According to the viewpoint of material survey, germanium-based MOSFET, which exhibits intrinsic high mobility, is considered a promising candidate for next-generation transistors. With the suitable introduction of stress-induced thin coating, such as silicon nitride contact etch stop layer (CESL), the electron mobility of devices can be further enhanced to compensate for the significant degeneration of lattice-mismatched stress resulting from rigorous dimensional shrinkage. The tensile CESL is commonly adopted to induce a biaxial tensile stress on the wide scope of n-type MOSFETs. However, the induced tensile stress that occurs along the transverse direction of a concerned device channel decreases the carrier mobility. Hence, this study proposes special layout designs with dummy gates placed on the transverse direction of the device channel. The effect of stress magnification from CESL coating on Ge-based n-type MOSFET is presented via a finite element analysis and a high-order piezoresistance model. Result shows that an enhanced carrier mobility gain of approximately 16.47% is obtained when a 50 nm-thick CESL with a tensile of 2.0 GPa is considered. [ABSTRACT FROM AUTHOR]