Methodology of determining the applicability range of the DPL model to heat transfer in modern integrated circuits comprised of FinFETs.

Abstract The main aim of this paper is to present the methodology for calculating the applicability range of the Dual-Phase-Lag model in integrated circuits (IC) made of different materials. Furthermore, analyses of requirements for using the Dual-Phase-Lag instead of the Fourier-Kirchhoff heat transfer model are described. All considerations are based on a transistor elementary cell including FinFETs in modern ICs. The obtained results have been analyzed in detail and compared. Moreover, the paper shows an important correction to the Neumann boundary condition required for consistency with the Dual-Phase-Lag equation. In addition, the simplified Dual-Phase-Lag model has also been presented in this paper. It is based on both the classical Fourier-Kirchhoff methodology and Dual-Phase-Lag approach. However, significant improvements related to time lags approximation have been proposed. This simplified model can be implemented in Finite Difference Method and Finite Element Method simulators based on two conjugate diffusion equations. Finally, the temperature distribution inside one- and three-dimensional FinFET structures has been determined based on Fourier-Kirchhoff and Dual-Phase-Lag models. Highlights • The applicability range of Dual-Phase-Lag (DPL) model for different materials is presented. • The 1-D and 3-D DPL model of 12 nm FinFET cell is delivered. • The simplified as well as harmonic conjugate diffusion DPL model is proposed. • The important correction to the Neumann boundary condition is proposed. • The cut-off frequency (bandwidth) estimation procedure is presented. [ABSTRACT FROM AUTHOR]