SOI-LDMOS Transistors With Optimized Partial n+ Buried Layer for Improved Performance in Power Amplifier Applications.

In this paper, for the first time, we demonstrate the improvement in power capability and safe operating area of silicon-on-insulator laterally double-diffused MOS (SOI-LDMOS) transistors for power amplifier applications by the introduction of a partial n+ buried layer (PNBL). The power capability of a transistor can be evaluated by ${P}_{\text {max}}/A$ , which is the maximum power per unit area that can be delivered by the transistor and is an important parameter for power amplifiers. ${P}_{\text {max}}$ is dependent on the snapback voltage (${V}_{\text {sb,QS}}$), OFF-state breakdown voltage (${V}_{\text {bd}, \mathrm{\scriptscriptstyle OFF}}$), and maximum current (${I}_{\text {max}}$) in the quasi-saturation regime of an LDMOS transistor. Increase of ${P}_{\text {max}}/A$ by the introduction of a PNBL in the SOI-LDMOS transistors is reported in this paper. The effects of variation of the length, thickness, and doping concentration of the PNBL on ${V}_{\text {sb,QS}}$ and ${P}_{\text {max}}/A$ are analyzed in detail. It is shown that by optimizing the doping and length of the PNBL layer, the maximum power output from the transistor can be made significantly higher than that of a conventional device without PNBL. A procedure to design the optimized structure is also presented. [ABSTRACT FROM AUTHOR]