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A Study on OTS-PCM Pillar Cell for 3-D Stackable Memory.

Authors :
Chien, Wei-Chih
Yeh, Chiao-Wen
Bruce, Robert L.
Cheng, Huai-Yu
Kuo, I. T.
Yang, Chih-Hsiang
Ray, A.
Miyazoe, Hiroyuki
Kim, W.
Carta, Fabio
Lai, Erh-Kun
BrightSky, Matthew J.
Lung, Hsiang-Lan
Source :
IEEE Transactions on Electron Devices. Nov2018, Vol. 65 Issue 11, p5172-5179. 8p.
Publication Year :
2018

Abstract

High endurance ovonic threshold switch (OTS, here, TeAsGeSiSe-based) is integrated with phase change memory (PCM, here, doped Ge2Sb2Te5) to form a 3-D stackable pillar-type device. With the help of an etch buffer layer and a damage-free pillar reactive-ion etching process, we successfully demonstrate one-selector (OTS)/one-resistor (PCM) (1S1R OTS-PCM) pillar device without OTS/PCM composition modification. High temperature 400 °C annealing tests show this 1S1R OTS-PCM pillar device is back end of line compatible. We report the fundamental behavior of the OTS and the operation scheme of the 1S1R OTS-PCM device. The new Vth read scheme is proposed and excellent electrical performance is demonstrated. It provides the fast turn ON/ OFF speed which enables 10-ns fast RESET speed. Program endurance greater than 109 cycles is achieved, and read endurance is higher than 1011 cycles. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
00189383
Volume :
65
Issue :
11
Database :
Academic Search Index
Journal :
IEEE Transactions on Electron Devices
Publication Type :
Academic Journal
Accession number :
132546212
Full Text :
https://doi.org/10.1109/TED.2018.2871197