Cite
A Comprehensive Study of a Single-Transistor Latch in Vertical Pillar-Type FETs With Asymmetric Source and Drain.
MLA
Lee, Seung-Wook, et al. “A Comprehensive Study of a Single-Transistor Latch in Vertical Pillar-Type FETs With Asymmetric Source and Drain.” IEEE Transactions on Electron Devices, vol. 65, no. 11, Nov. 2018, pp. 5208–12. EBSCOhost, https://doi.org/10.1109/TED.2018.2869670.
APA
Lee, S.-W., Kim, S.-Y., Hwang, K.-M., Jin, I. K., Hur, J., Kim, D.-H., Son, J. W., Kim, W.-K., & Choi, Y.-K. (2018). A Comprehensive Study of a Single-Transistor Latch in Vertical Pillar-Type FETs With Asymmetric Source and Drain. IEEE Transactions on Electron Devices, 65(11), 5208–5212. https://doi.org/10.1109/TED.2018.2869670
Chicago
Lee, Seung-Wook, Seong-Yeon Kim, Kyu-Man Hwang, Ik Kyeong Jin, Jae Hur, Do-Hyun Kim, Jun Woo Son, Wu-Kang Kim, and Yang-Kyu Choi. 2018. “A Comprehensive Study of a Single-Transistor Latch in Vertical Pillar-Type FETs With Asymmetric Source and Drain.” IEEE Transactions on Electron Devices 65 (11): 5208–12. doi:10.1109/TED.2018.2869670.