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Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines.
- Source :
-
Journal of Parallel & Distributed Computing . Jan2019, Vol. 123, p118-129. 12p. - Publication Year :
- 2019
-
Abstract
- Abstract Advancements in CMOS technology led to the increase in number of processing cores on a single chip. Communication between different cores in such multicore systems is facilitated by an underlying interconnect. Due to the limitations of traditional bus-based system Network on Chip (NoC) based interconnect is the most acceptable cost effective framework for inter-core communication. A packet in an NoC travels through a sequence of intermediate routers before arriving at its destination. As the size of NoC scales high, the average number of intermediate routers that a packet traverse also increases. This results in higher packet latency which degrades application performance. In this work, we introduce cost effective adaptive routing techniques that can forward long distance packets through specialized channels made of Transmission Line (TL). These extra TLs introduced in the chip reduce the diameter of the network thereby reducing average packet latency. We propose two novel router architectures; SBTR and e-SBTR that reduce packet latency by reducing the number of intermediate hops. We use PARSEC benchmark and SPEC CPU 2006 benchmark mixes to evaluate the performance of our proposed techniques. SBTR and e-SBTR reduce average packet latency by 7.9% and 25% respectively. Both the techniques also reduce average hop count by 8.13% and 27.6% respectively. We also observe that our proposed technique e-SBTR performs better than the state-of-the-art Express Virtual Channel technique in terms of packet latency and hop count respectively. Highlights • Long distance on-chip communication degrades the performance of NoC in CMP. • We propose a hybrid NoC architecture with high speed Transmission Line (TL). • An adaptive routing technique (SBTR) is proposed to send long distance packets with TL. • An improved hybrid mechanism called e-SBTR is also proposed in this paper. • The proposed techniques are compared and combined with an existing technique. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 07437315
- Volume :
- 123
- Database :
- Academic Search Index
- Journal :
- Journal of Parallel & Distributed Computing
- Publication Type :
- Academic Journal
- Accession number :
- 132870982
- Full Text :
- https://doi.org/10.1016/j.jpdc.2018.09.009