Double-precision Dual Mode Logic carry-save multiplier.

Abstract In this paper, a double-precision carry-save adder (CSA)-based array multiplier is designed using the Dual Mode Logic (DML) approach in a commercial 65-nm low-power CMOS technology. DML typically allows on-the-fly controllable switching at the gate level between static and dynamic operation modes. The proposed multiplier exploits this unique ability of DML to efficiently trade performance and energy consumption when considering on-demand double-precision (8 × 8-bit or 16 × 16-bit) operations. This occurs in the DML multiplier working in a mixed operation mode, i.e., by employing the static and dynamic mode for lower and higher precision operations, respectively. In fact, the use of the dynamic mode for higher precision operations ensures higher performance as compared to the standard CMOS circuit (16% gain on average) at the cost of higher energy consumption. Such energy penalty is counterbalanced at lower precision operations where the static mode is enabled in the DML circuit. Overall, the adoption of the mixed operation mode in the proposed DML multiplier proves to be beneficial to achieve a better performance/energy trade-off with respect to the standard CMOS implementation and to the case when using either the static or the dynamic mode for both operations at the two different precisions. When compared to its CMOS counterpart, our DML design operating in the mixed mode exhibits an average improvement of 15% in terms of energy-delay product (EDP) under wide-range supply voltage scaling. Such benefit is maintained over process-voltage-temperature (PVT) variations. Highlights • A double-precision (8 × 8-bit or 16 × 16-bit) multiplier is designed using the Dual Mode Logic (DML) in a 65-nm CMOS technology. • This multiplier works in a mixed operation mode by switching between static and dynamic mode according to the different precision. • Such mixed mode allows boosting the gain in energy-delay product (EDP) of the DML circuit with respect to its CMOS counterpart. • When compared to the CMOS circuit, our DML design working in the mixed mode exhibits an average gain of 15% in terms of EDP. • Such benefit is maintained over a wide range of process-voltage-temperature (PVT) variations. [ABSTRACT FROM AUTHOR]