Optimization and Scaling of Ge-Pocket TFET.

TFETs are promising candidates for future low-power logic applications because of their potential for outperforming conventional MOSFETs under reduced supply voltage (${V} _{\textsf {DD}}$). Among all material systems currently being explored, group IV semiconductor SiGe holds the most potential due to its very large scale integration (VLSI) compatibility, mature synthesis techniques, and tunable bandgap, making it more likely to be adopted for future VLSI technologies. It has been shown experimentally that the on-state current (${I} _{\textsf {on}}$) of SiGe TFETs improves significantly with the increasing Ge content. However, increasing the Ge content leads to excessive leakage in the off-state and poses a challenge to the pseudomorphic growth of SiGe. In this paper, the concept of Ge-pocket TFET with a counter-doped pocket is proposed. By confining Ge to the pocket region, the proposed structure circumvents those problems. Both the steep subthreshold swing and high ${I} _{\textsf {on}}$ can be achieved. The proposed TFET also demonstrates excellent scalability in terms of physical gate length (${L} _{\textsf {gate}}$) and ${V} _{\textsf {DD}}$ , which makes it a promising replacement of conventional MOSFETs for low-power logic applications. [ABSTRACT FROM AUTHOR]