An evaluation system for logic functions based on decision diagrams.

The authors propose a system to evaluate multiple output logic functions using hardware based on a decision diagram. In addition, the authors propose a PMDD (Paged reduced ordered Multivalued Decision Diagram) as a data structure. Methods to evaluate a logic function in hardware include methods based on an SBDD (Shared reduced ordered Binary Decision Diagram). The method based on a PMDD evaluates multiple output functions using several computational units, and as a result is faster compared to methods based on an SBDD. The multiple output logic function to be created is represented using a PMDD and stored in memory. Then a control circuit which can search the PMDD is added. The authors compare the memory capacity and processing time required for various benchmark functions for the SBDD and their PMDD. © 2004 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 87(9): 73–81, 2004; Published online in Wiley InterScience (<URL>www.interscience.wiley.com</URL>). DOI 10.1002/ecjc.20097 [ABSTRACT FROM AUTHOR]