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A 25-GS/s 6-bit time-interleaved SAR ADC with design-for-test memory in 40-nm low-leakage CMOS.
- Source :
-
International Journal of Electronics . Jun2019, Vol. 106 Issue 6, p829-845. 17p. - Publication Year :
- 2019
-
Abstract
- This paper presents a 25-GS/s 6-bit time-interleaved (TI) SAR ADC in a 40-nm CMOS low-leakage (LL) process. The prototype utilizes 4 × 12 hierarchical sampling architecture to reduce the complexity of track-and-hold circuits and the timing skew calibration. The single-channel SAR ADC adopts asynchronous processing with two alternate comparators. A partially active reference voltage buffer is designed to reduce the power consumption. The method based on sinusoidal signal approximation is employed to calibrate timing skew errors. To characterize the ultra-high-speed ADC, an on-chip design-for-test memory is designed. At 25 GS/s, the ADC achieves the SNDR of 32.18 dB for low input frequency and 27.28 dB for Nyquist frequency. The chip consumes 800 mW and occupies 1.3 × 2.6 mm2, including the TI ADC core and memory. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00207217
- Volume :
- 106
- Issue :
- 6
- Database :
- Academic Search Index
- Journal :
- International Journal of Electronics
- Publication Type :
- Academic Journal
- Accession number :
- 135500898
- Full Text :
- https://doi.org/10.1080/00207217.2019.1570557