Back to Search
Start Over
Interpreting Local Variables in AMS Assertions During Simulation.
- Source :
-
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems . May2019, Vol. 38 Issue 5, p980-984. 5p. - Publication Year :
- 2019
-
Abstract
- The support for local variables in SystemVerilog assertions significantly enhances its expressive power. Handling local variables in analog and mixed-signal (AMS) extensions of assertion languages is tricky due to the dense time interpretation of AMS assertions, and has not been adequately treated in existing literature. This paper presents an approach for interpreting local variables in AMS assertions during simulation and a tool flow that works with standard mixed-mode simulators. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 02780070
- Volume :
- 38
- Issue :
- 5
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems
- Publication Type :
- Academic Journal
- Accession number :
- 136101429
- Full Text :
- https://doi.org/10.1109/TCAD.2018.2824288