Cite
Half-select free bit-line sharing 12T SRAM with double-adjacent bits soft error correction and a reconfigurable FPGA for low-power applications.
MLA
Sharma, Vishal, et al. “Half-Select Free Bit-Line Sharing 12T SRAM with Double-Adjacent Bits Soft Error Correction and a Reconfigurable FPGA for Low-Power Applications.” AEU: International Journal of Electronics & Communications, vol. 104, May 2019, pp. 10–22. EBSCOhost, https://doi.org/10.1016/j.aeue.2019.02.018.
APA
Sharma, V., Bisht, P., Dalal, A., Gopal, M., Vishvakarma, S. K., & Chouhan, S. S. (2019). Half-select free bit-line sharing 12T SRAM with double-adjacent bits soft error correction and a reconfigurable FPGA for low-power applications. AEU: International Journal of Electronics & Communications, 104, 10–22. https://doi.org/10.1016/j.aeue.2019.02.018
Chicago
Sharma, Vishal, Pranshu Bisht, Abhishek Dalal, Maisagalla Gopal, Santosh Kumar Vishvakarma, and Shailesh Singh Chouhan. 2019. “Half-Select Free Bit-Line Sharing 12T SRAM with Double-Adjacent Bits Soft Error Correction and a Reconfigurable FPGA for Low-Power Applications.” AEU: International Journal of Electronics & Communications 104 (May): 10–22. doi:10.1016/j.aeue.2019.02.018.