Two Capacitance States Memory Characteristic in Metal–Oxide–Semiconductor Structure Controlled by an Outer MOS-Gate Ring.

In this paper, an inner ultrathin oxide metal–oxide–semiconductor (MOS) capacitor is fabricated with another outer MOS-gate ring as a coupling controller. Capacitance–voltage characteristics of inner MOS capacitor show that the excess minority carriers supplied from the outer MOS-gate ring can efficiently change the inner capacitance (${C} _{\text {inner}}$). It is observed that outer MOS-gate ring under the conditions at floating and at ground has quite different coupling effects on ${C} _{\text {inner}}$ when the inner MOS is biased at 1 V. Comparing to ${V} _{\text {outer}} = \text {floating}$ , ${C} _{\text {inner}}$ reduces significantly when ${V} _{\text {outer}} = {0}$ V at 1k Hz. The transient behavior of ${C} _{\text {inner}}$ as ${V} _{\text {outer}}$ changes from 0 V to floating is long enough to read, and the difference of two capacitance values can be regarded as two states. As a result, a two capacitance states operation is proposed for possible memory application. Based on the experimental results, the possible memory cell configuration is designed. Comparing to the present emerging memories, since the two states in this paper are in conditions of floating and 0 V, ultralow power is consumed, which is believed a promising concept for future memory application. [ABSTRACT FROM AUTHOR]