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3-D Stacked Synapse Array Based on Charge-Trap Flash Memory for Implementation of Deep Neural Networks.
- Source :
-
IEEE Transactions on Electron Devices . Jan2019, Vol. 66 Issue 1, p420-427. 8p. - Publication Year :
- 2019
-
Abstract
- This paper proposes a synaptic device based on charge-trap flash memory that has good CMOS compatibility and superior reliability characteristics compared with other synaptic devices. Using hot-electron injection and hot-hole injection, we designed operation methods to implement gradual conductance modulation and spike-timing-dependent plasticity. We demonstrate the feasibility of the device for neuromorphic applications through both a device-level technology computer-aided design simulation and a system-level MATLAB simulation. For the first time, we also propose a 3-D stacked synapse array and present the structure, operation, and process methods. The proposed array architecture features a small area and low process cost and could be a novel solution for neuromorphic systems for implementing deep neural networks. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 66
- Issue :
- 1
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 137215182
- Full Text :
- https://doi.org/10.1109/TED.2018.2881972