Thermal-Aware Shallow Trench Isolation Design Optimization for Minimizing ${I}_{OFF}$ in Various Sub-10-nm 3-D Transistors.

In this paper, we have devised on shallow trench isolation (STI) design considering leakage current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) in Bulk/silicon on insulator (SOI) FinFET and vertical FET (VFET). The ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ tendency is considered in terms of the interface trap density (${D}_{\textsf {it}}$) difference depending on the STI material type and STI thickness. In the case of Bulk FinFET, the STI design for each of high performance (HP) and low power (LP) is presented. On the other hand, in the case of SOI FinFET and VFET, STI designs which do not distinguish HP/LP are presented. Max lattice temperature (${T}_{\textsf {L,max}}$)/thermal resistance (${R}_{\textsf {th}}$)/on current (${I}_{ \mathrm{\scriptscriptstyle ON}}$) degradation rate according to STI design in each structure are also analyzed. Finally, we compare the hot carrier injection (HCI)/bias temperature instability (BTI) lifetime as a function of the device temperature which is varied depending on STI design. In conclusion, our proposed STI design effectively reduces the self-heating effect in each structure and increases the HCI/BTI lifetime accordingly. [ABSTRACT FROM AUTHOR]