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Data-path aware high-level ECO synthesis.
- Source :
-
Integration: The VLSI Journal . Mar2019, Vol. 65, p88-96. 9p. - Publication Year :
- 2019
-
Abstract
- Engineering Change Order (ECO) at Register Transfer Level (RTL) has been widely investigated by researchers, but at a higher level of abstraction than RTL, it is not properly addressed. Applying ECO using conventional HLS tools may result in a heavily different RTL in comparison with the original one. In order to minimize this difference, we have proposed a new high-level synthesis methodology, which considers the resulting data-path and its difference from the original one during scheduling and binding of the operations. Experimental results show that our proposed methodology makes only 6.9% changes in the connections of the original data-path in contrast to existing HLS tools, which alter 25.16% of the connections on average. Our methodology exploits 66% less spare cells than the existing HLS tools and makes no change in functional units and registers. • Considering metal mask ECO, by restricting changes only to the connections between resources of the original data-path. • Using difference between the new data-path and original as an optimization target during integrated scheduling and binding. • Proposing a heuristic partitioning method to break up the large synthesis problem in order to tackle scalability issue. [ABSTRACT FROM AUTHOR]
- Subjects :
- *HEURISTIC
*SCALABILITY
Subjects
Details
- Language :
- English
- ISSN :
- 01679260
- Volume :
- 65
- Database :
- Academic Search Index
- Journal :
- Integration: The VLSI Journal
- Publication Type :
- Academic Journal
- Accession number :
- 137265138
- Full Text :
- https://doi.org/10.1016/j.vlsi.2018.11.006