Impact of different localized trap charge profiles on the short channel double gate junctionless nanowire transistor based inverter and Ring Oscillator circuit.

In this paper, the reliability issues due to localized charges on Double Gate Junctionless Nanowire Transistor (DG-JNT) based circuits are investigated. The localized/fixed charges come into existence at the interface of substrate and oxide in the device during the manufacturing due to radiation, stress, process and hot carriers damage which significantly alters various characteristics of the device. The damage due to different profiles of localized charges on several parameters of DG-JNT based P-MOSFET is analyzed. Also, for analog circuit application, this work explicitly reports the comprehensive analysis of localized charge profiles on DG- JNT based CMOS inverter and three Stage Ring Oscillator circuit at 20 nm Gate length. The simulated results are obtained using Silvaco Atlas, TCAD device simulator. [ABSTRACT FROM AUTHOR]