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Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation.
- Source :
-
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems . Aug2019, Vol. 38 Issue 8, p1385-1398. 14p. - Publication Year :
- 2019
-
Abstract
- In this paper, a graph-constrained sparse performance modeling method is proposed for analog circuit optimization. It builds sparse polynomial models constrained by an acyclic graph. These models can be used to solve analog optimization problems within local design spaces by using convex semidefinite programming relaxation both efficiently and robustly. Our numerical examples demonstrate that the proposed modeling and optimization method can quickly and accurately converge to a superior solution for analog circuits while the conventional method fails to work. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 02780070
- Volume :
- 38
- Issue :
- 8
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems
- Publication Type :
- Academic Journal
- Accession number :
- 137645910
- Full Text :
- https://doi.org/10.1109/TCAD.2018.2848590