Back to Search Start Over

Exploiting Shared-Memory to Steer Scalability of Fault Simulation Using Multicore Systems.

Authors :
Hadjitheophanous, Stavros
Neophytou, Stelios N.
Michael, Maria K.
Source :
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Aug2019, Vol. 38 Issue 8, p1466-1479. 14p.
Publication Year :
2019

Abstract

Current and future multicore architectures can significantly accelerate the performance of test automation procedures depending on the underlying architecture and the scalability of their algorithms. This paper proposes a new parallel methodology targeting the fault simulation problem, for shared memory multicore systems, that maintains scalability with the increase of the number of cores. The method is based on a simple single thread process that allows focusing on the optimization of the parallelization process in different dimensions. Additionally, a number of optimizations are incorporated in the approach to control fault dropping and to avoid unnecessary work. The reported experimental results, for both random and deterministic test sets, demonstrate the scalability of the method. As the number of cores increases, the reported speed-up increases proportionally, where comparable recent methods report saturation or even reduction of the obtained speed-up. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
02780070
Volume :
38
Issue :
8
Database :
Academic Search Index
Journal :
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems
Publication Type :
Academic Journal
Accession number :
137645917
Full Text :
https://doi.org/10.1109/TCAD.2018.2855131