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Synchronous Adaptive Resolver-to-Digital Converter for FPGA-Based High-Performance Control Loops.
- Source :
-
IEEE Transactions on Instrumentation & Measurement . Oct2019, Vol. 68 Issue 10, p3972-3982. 11p. - Publication Year :
- 2019
-
Abstract
- This paper deals with a gain scheduling synchronous demodulation scheme useful to obtain speed and position measurements from resolver position sensors. The proposed algorithm is devoted to a field-programmable gate array implementation in order to provide the elaborated information for very low latency control loops. The presented design allows getting accurate estimations in a wide range of rotational speeds without requiring costly off-the-shelf integrated circuits and leads to higher accuracy at low speed if compared to commercial solutions. To this purpose, the resolver excitation circuit has been simplified working directly with a square wave signal, and the resolver frequency behavior due to the nonsinusoidal excitation has been considered. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189456
- Volume :
- 68
- Issue :
- 10
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Instrumentation & Measurement
- Publication Type :
- Academic Journal
- Accession number :
- 138733413
- Full Text :
- https://doi.org/10.1109/TIM.2018.2884556