Performance Assessment of the Charge-Plasma-Based Cylindrical GAA Vertical Nanowire TFET With Impact of Interface Trap Charges.

In this article, a charge-plasma (CP)-based gate-all-around (GAA) silicon vertical nanowire tunnel field-effect transistor (NWTFET) is proposed. The effects of interface trap charges (ITCs) on dopingless (DL) NW-based device have been addressed for the first time. CP technique is used to induce charge carriers within the drain/source regions by depositing layers of metals with specific work function. Linearity performance parameters such as higher order harmonic distortions (HDs), intermodulation distortions (IMDs), and interception points are calculated including the effects of ITCs on the cylindrical channel–surround gate–oxide interface. This work shows that positive ITCs can help in improving the device characteristics, whereas negative ITCs degrade the device performance. The ON-state current to OFF-state current ratio decreases for either polarity of ITCs. The ON-state current has been improved by approximately 50% with higher positive ITCs. The presence of positive ITCs in DL NWTFET improves the driving capability to be used for analog applications. The linearity parameters tend to improve with positive ITCs and degrade with negative ITCs. The proposed device has reached the same cutoff frequency at lower operating gate bias (approximately 0.8 V) with half the threshold voltage for higher positive ITCs. [ABSTRACT FROM AUTHOR]