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A low-power dynamic comparator for low-offset applications.

Authors :
Khorami, Ata
Saeidi, Roghayeh
Sachdev, Manoj
Sharifkhani, Mohammad
Source :
Integration: The VLSI Journal. Nov2019, Vol. 69, p23-30. 8p.
Publication Year :
2019

Abstract

In this paper, a low-power method for double-tail comparators is introduced. Using the proposed method, the power consumption of the pre-amplifier which is the dominant part is reduced considerably. Thanks to this method, the pre-amplifier is not able to draw more than required amount of power, therefore, the power is saved. Post layout and corner simulation results show the power consumption is reduced by about 40%. Moreover, several Monte-Carlo (M) simulations suggest the proposed method results in about 20% offset reduction at the cost of 5% area and 10% speed degradation. • In dynamic comparators, the pre-amplifier amplifies the input differential signal to some extent then the latch finalizes the comparison. After some moment from the latch activation, the pre-amplifier is wasting power and sometimes reduces the gain worsening the power consumption and offset voltage. The aim of the proposed comparator is to overcome this issue. In low-offset comparators, the sizing of the input transistors of the pre-amplifier is chosen large for matching purposes so that the pre-amplifier consumes the dominant part of the total power consumption making it a good candidate to work on for low-power applications. In this paper, a low power method for dynamic comparators is presented using which the power consumption of the pre-amplifier is controlled in a proper way. Therefore, not only the power is saved but also the input referred offset voltage is improved. • In the paper, analytical derivations are presented to quantify the amount of power saving. Simulations showed the derivations are consistent with the circuit. The proposed method is able to reduce the power consumption by about 30%-40% and the offset voltage by about 20%. Post layout simulation of the RC-CC extracted circuit confirms the benefits of the proposed comparator. • The proposed method is applicable to different types of the double tail comparators. This method is simple yet effective in power reduction. [ABSTRACT FROM AUTHOR]

Subjects

Subjects :
*COMPARATOR circuits
*COST control

Details

Language :
English
ISSN :
01679260
Volume :
69
Database :
Academic Search Index
Journal :
Integration: The VLSI Journal
Publication Type :
Academic Journal
Accession number :
139543165
Full Text :
https://doi.org/10.1016/j.vlsi.2019.07.001