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Invisible-Scan: A Design-for-Testability Approach for Functional Test Sequences.

Authors :
Pomeranz, Irith
Source :
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Dec2019, Vol. 38 Issue 12, p2357-2365. 9p.
Publication Year :
2019

Abstract

Functional test sequences can detect defects that are not detected by scan-based tests, but overall, achieve a lower gate-level fault coverage than scan-based tests. Design-for-testability (DFT) approaches for functional test sequences cause the sequences to deviate from functional operation conditions in arbitrary ways over the entire design. This paper introduces the concept of invisible-DFT as a DFT approach for functional test sequences, where the effects of activating the DFT logic are confined to selected logic blocks. This paper develops an invisible-scan approach. Considering a single logic block, the procedure described in this paper inserts scan shift cycles into a functional test sequence while maintaining the same primary input and output sequences for the logic block. This makes the activation of the DFT logic invisible to other logic blocks. The procedure allows a limited number of primary output vectors to be corrected for this purpose. Experimental results are presented to demonstrate the increase in fault coverage that can be achieved by invisible-scan. [ABSTRACT FROM AUTHOR]

Subjects

Subjects :
*LOGIC circuits

Details

Language :
English
ISSN :
02780070
Volume :
38
Issue :
12
Database :
Academic Search Index
Journal :
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems
Publication Type :
Academic Journal
Accession number :
139785892
Full Text :
https://doi.org/10.1109/TCAD.2018.2878176