A Method to Reduce the Circuit Scale for Systolic Arrays and Its Application to Reed-Solomon Codecs.

The systolic array is a scheme for parallel processing and provides an architecture which is suited to a high-speed operation. Consequently, the systolic array has been applied to the system for which the high-speed processing is required, but not to the system for which the reduction of the circuit scale is required. This paper demonstrates that the principle of the systolic array can be applied as a means of reducing the circuit scale. By the proposed method, the circuit scale can be reduced in the system based on the systolic array, without an appreciable modification of the connection in the array and the control. This paper discusses the Reed-Solomon (RS) coder-decoder based on the systolic array as an example, and shows that the circuit scale can be reduced simply. By this system, the RS coder-decoder can be realized in a simple way by the small circuit scale, corresponding to the processing speed of the system. [ABSTRACT FROM AUTHOR]