Design of hybrid flash-SAR ADC using an inverter based comparator in 28 nm CMOS.

This paper presents a hybrid design of flash based successive approximation register (SAR) analog-to-digital converter (ADC) with a resolution of 6 bits, operating at 1 GS/s. The dynamic comparator in traditional architecture is replaced by an inverter based comparator, for an energy efficient comparison. A segmented spilt capacitor array charge redistribution digital-to-analog-converter (CDAC) is used to achieve improved linearity, power, speed and area. Further, a 3 bit per clock cycle approach is adopted to achieve fast conversion time. The hybrid flash-SAR ADC has been designed and simulated in a standard 28 nm CMOS technology with V DD of 0.9 V and 1 GS/s of sampling rate. The designed ADC achieves a peak SNDR of 35.56 dB and an SFDR of 40.81 dB. The design achieves 5.61 effective number of bits (ENOB) with 2.33 mW of power consumption and figure-of-merit (FOM) of 47.7 fJ/conversion. [ABSTRACT FROM AUTHOR]