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Automated I/O Library Generation for Interposer-Based System-in-Package Integration of Multiple Heterogeneous Dies.
- Source :
-
IEEE Transactions on Components, Packaging & Manufacturing Technology . Jan2020, Vol. 10 Issue 1, p111-122. 12p. - Publication Year :
- 2020
-
Abstract
- System-in-package (SiP) integration of multiple dies in a single package can achieve much higher performance than onboard integration of integrated circuits (ICs) while reducing the design cost/effort compared to a large system on chips (SoCs). However, a major challenge in the design of SiPs with many dies is automated design and insertion of input/output (I/O) cells to minimize energy and delay of the wire traces. This article presents an automated cell library generation flow for all-digital I/O circuits for SiP integration. Given parameterized models of SiP wire traces, our method automatically designs, optimizes, and generates layouts of I/O cells for delay/energy minimization. The proposed flow is demonstrated on interposer-based SiP integration considering 28-nm CMOS technology and 65-nm BEOL technology. Given a multidie SiP design and associated interposer wire traces, this article demonstrates that automated I/O library cell generation can reduce the maximum die-to-die communication delay or energy. We demonstrate the proposed flow for various interposer parameters and SiP designs to show the feasibility of chip-interposer codesign. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 21563950
- Volume :
- 10
- Issue :
- 1
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Components, Packaging & Manufacturing Technology
- Publication Type :
- Academic Journal
- Accession number :
- 141257019
- Full Text :
- https://doi.org/10.1109/TCPMT.2019.2953659