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A Single Event Upset Resilient Latch Design with Single Node Upset Immunity.

Authors :
Dai, Xixi
Wang, Haibin
Chu, Jiamin
Liu, Zhi
Cai, Li
Yan, Kang
Source :
Journal of Electronic Testing. Dec2019, Vol. 35 Issue 6, p909-916. 8p.
Publication Year :
2019

Abstract

In this paper, a latch design with single node immunity to single event upsets during the hold state is proposed. This structure is based on the original Quatro latch and have two more redundant storage nodes. Compared with the reference, this structure is able to recover if any of these nodes is struck by ion particles during the hold state and it also has improved multiple node upset performance. Simulations and laser experiment results have validated its effectiveness of SEU resilience by having a larger laser energy threshold for upset and lower SEU error counts compared with the reference. The power, area, and delay penalties are 86%, 48%, and 64% respectively; they are as a consequence of six more transistors added to the latch. [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
09238174
Volume :
35
Issue :
6
Database :
Academic Search Index
Journal :
Journal of Electronic Testing
Publication Type :
Academic Journal
Accession number :
141414592
Full Text :
https://doi.org/10.1007/s10836-019-05823-x