A sensitivity-enhanced capacitance readout circuit with symmetric cross-coupling structure.

This paper presents a proposed capacitance readout circuit that enables a quadrupled (x4) output strength. A symmetric cross-coupling structure is proposed to amplify the voltage difference between two adjacent channels; hence, the detected signal can be integrated twice every clock cycle. Compared with conventional schematics, the proposed readout circuit shows an increased output strength for integration times within dozens of μs. In addition, the measurements show that the integrator resistors should be less than 1 kΩ to suppress the resistance–capacitance delay effects. Although the proposed capacitance readout circuit is implemented using discrete transistors, it has a good signal integrity at an operating clock cycle of 100 µs. Therefore, the proposed readout circuit is a promising way to detect small capacitance variations with short integration times. [ABSTRACT FROM AUTHOR]