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A 32-Step Phase-Compensated Spread-Spectrum RF-PLL With 19.44-dB EMI Reduction and 10-fs Extra RMS Jitter.
- Source :
-
IEEE Transactions on Microwave Theory & Techniques . Apr2020, Vol. 68 Issue 4, p1564-1575. 12p. - Publication Year :
- 2020
-
Abstract
- Spread-spectrum clocking (SSC) is an active solution to attenuate electromagnetic interference (EMI) in Gb/s serial communication systems by slightly modulating the phase-locked loop (PLL) output clock frequency. This article presents a phase-compensated spread-spectrum clock generator (SSCG) with the state-of-the-art EMI reduction and clock rms jitter performance. A 32-slice scaled resistor-based buffer is proposed to realize the phase interpolator (PI). The proposed design has no static current and low complexity without active device matching requirement. The 32-slice PI structure can achieve a simulated 22-dB EMI reduction with a 32-step triangular modulation profile. The proposed SSCG chip with a charge-pump-based fractional- $N$ radio frequency (RF)-PLL and a source-series-terminated (SST) driver is fabricated using a 55-nm CMOS process. Measurement result shows that EMI reduction of the 5-GHz output clock power spectrum is 19.44 dB under 0.5% down-spread. The rms jitters with SSC-off and SSC-on, adopting a second-order clock recovery in oscilloscope, are 630 and 640 fs, respectively. The normalized power consumption is 9.3 mW/GHz, and the core area occupation is 0.092 mm2. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189480
- Volume :
- 68
- Issue :
- 4
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Microwave Theory & Techniques
- Publication Type :
- Academic Journal
- Accession number :
- 143313816
- Full Text :
- https://doi.org/10.1109/TMTT.2019.2960227