Cite
Drain–Erase Scheme in Ferroelectric Field-Effect Transistor—Part I: Device Characterization.
MLA
Wang, Panni, et al. “Drain–Erase Scheme in Ferroelectric Field-Effect Transistor—Part I: Device Characterization.” IEEE Transactions on Electron Devices, vol. 67, no. 3, Mar. 2020, pp. 955–61. EBSCOhost, https://doi.org/10.1109/TED.2020.2969401.
APA
Wang, P., Wang, Z., Shim, W., Hur, J., Datta, S., Khan, A. I., & Yu, S. (2020). Drain–Erase Scheme in Ferroelectric Field-Effect Transistor—Part I: Device Characterization. IEEE Transactions on Electron Devices, 67(3), 955–961. https://doi.org/10.1109/TED.2020.2969401
Chicago
Wang, Panni, Zheng Wang, Wonbo Shim, Jae Hur, Suman Datta, Asif Islam Khan, and Shimeng Yu. 2020. “Drain–Erase Scheme in Ferroelectric Field-Effect Transistor—Part I: Device Characterization.” IEEE Transactions on Electron Devices 67 (3): 955–61. doi:10.1109/TED.2020.2969401.