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Drain-Erase Scheme in Ferroelectric Field Effect Transistor—Part II: 3-D-NAND Architecture for In-Memory Computing.
- Source :
-
IEEE Transactions on Electron Devices . Mar2020, Vol. 67 Issue 3, p962-967. 6p. - Publication Year :
- 2020
-
Abstract
- Ferroelectric-doped HfO2-based ferroelectric field-effect transistors (FeFETs) are being actively explored as emerging nonvolatile memory (NVM) devices with the potential for in-memory computing. In this two-part article, we explore the feasibility of the FeFET-based 3-D NAND architecture for both in situ training and inference. To address the challenge of erase-by-block in a NAND-like structure, we propose and experimentally demonstrate the drain-erase scheme to enable the individual cell’s program/erase/inhibition, which is necessary for individual weight updates in in situ training. We described the device characterization of different drain-erase conditions and results in Part I. The array-level design for this drain-erase scheme for both AND-type and NAND-type array is addressed in this Part II. A 3-D vertical channel FeFET array architecture is proposed to accelerate the vector-matrix multiplication (VMM). 3-D timing sequence of the weight update rule is designed and verified through the 3-D-array-level SPICE simulation. Finally, the VMM operation is simulated in a 3-D NAND-like FeFET array. [ABSTRACT FROM AUTHOR]
- Subjects :
- *FIELD-effect transistors
*FERROELECTRICITY
*NONVOLATILE memory
*FLASH memory
Subjects
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 67
- Issue :
- 3
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 143315799
- Full Text :
- https://doi.org/10.1109/TED.2020.2969383