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Small-Signal Modeling and Design of Phase-Locked Loops Using Harmonic Signal-Flow Graphs.
- Source :
-
IEEE Transactions on Energy Conversion . Jun2020, Vol. 35 Issue 2, p600-610. 11p. - Publication Year :
- 2020
-
Abstract
- This article introduces signal-flow graphs for linear time-periodic systems to streamline and visually describe the frequency-domain modeling of complex phase-locked loop (PLL) systems used in grid-connected converters. Small-signal modeling using the proposed graphs is demonstrated for two commonly used single-phase PLL structures: SOGI-PLL and Park-PLL. Loop-gain models are developed for these PLLs to evaluate how an orthogonal signal generator (OSG), which is required in single-phase PLLs using the synchronous reference frame (SRF) architecture, modifies the PLL loop gain compared to that of a three-phase SRF-PLL, which does not require an OSG. It is shown that the OSG in the SOGI-PLL and Park-PLL introduces a significant phase lag in the PLL loop gain, limiting the maximum bandwidth for which either PLL can be designed. Slow-frequency adaptation (SFA) of OSG is proposed to mitigate the influence of the OSG dynamics on the PLL loop gain. Experimental results are presented to validate the developed loop-gain models and show that the proposed SFA-SOGI-PLL and SFA-Park-PLL have better transient performance, they do not suffer from the bandwidth limit, and they preserve the steady-state performance of the standard SOGI-PLL and Park-PLL. [ABSTRACT FROM AUTHOR]
- Subjects :
- *PHASE-locked loops
*SIGNAL generators
*PERFORMANCE standards
*LINEAR systems
Subjects
Details
- Language :
- English
- ISSN :
- 08858969
- Volume :
- 35
- Issue :
- 2
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Energy Conversion
- Publication Type :
- Academic Journal
- Accession number :
- 143386089
- Full Text :
- https://doi.org/10.1109/TEC.2019.2954112