A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology.

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6 GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180 nm CMOS process with supply voltage of 1.8 V. The phase noise of VCO is − 1 3 7 dBc/Hz at an offset frequency of 100 MHz. The reference clock of 25 MHz synthesizes the output clock of 1.6 GHz with rms jitter of 0.642 ps. [ABSTRACT FROM AUTHOR]