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A 4-μm Diameter SPAD Using Less-Doped N-Well Guard Ring in Baseline 65-nm CMOS.
- Source :
-
IEEE Transactions on Electron Devices . May2020, Vol. 67 Issue 5, p2223-2225. 3p. - Publication Year :
- 2020
-
Abstract
- This brief reports a small size single-photon avalanche diode (SPAD) in baseline 65-nm CMOS suitable for low-cost time-of-flight application with high spatial resolution. By exploiting the less-doped n-well region to surround the vertical p-well/deep-n-well multiplication region, the electric field at the SPAD periphery can be reduced without process modifications while avoiding premature lateral breakdown. Validated using TCAD simulations, the fabricated 4-μm diameter SPAD device exhibits a compact device size with a low dark count (73 cps/μm2 at 20 °C) and a high fill factor (17.7%) using 65-nm baseline CMOS, while demonstrating competitive performance when compared with the state of the art. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 67
- Issue :
- 5
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 143858010
- Full Text :
- https://doi.org/10.1109/TED.2020.2982701