A time-interleaved pipelined ADC with ultra high speed sampling.

Based on a standard 0.18μm BiCMOS process, a 12 bit 2GSps ADC is achieved using time-interleaved pipelined architecture in this work. The DC offset caused by the mismatch of ADC channels is removed due to the application of digital calibration technology, which improves the performance of the ADC. The power supply voltage is 1.8 V and the power consumption is 100 mW for each lane. The measurement results indicated that the circuit in this paper can be used in multi-channel time-domain interleaved pipelined ADC architecture to achieve a 2GSps ultra high speed ADC. [ABSTRACT FROM AUTHOR]