A fast locking and low jitter hybrid ADPLL architecture with bang bang PFD and PVT calibrated flash TDC.

MLA

Sahani, Jagdeep Kaur, et al. “A Fast Locking and Low Jitter Hybrid ADPLL Architecture with Bang Bang PFD and PVT Calibrated Flash TDC.” AEU: International Journal of Electronics & Communications, vol. 124, Sept. 2020, p. N.PAG. EBSCOhost, https://doi.org/10.1016/j.aeue.2020.153344.

APA

Sahani, J. K., Singh, A., & Agarwal, A. (2020). A fast locking and low jitter hybrid ADPLL architecture with bang bang PFD and PVT calibrated flash TDC. AEU: International Journal of Electronics & Communications, 124, N.PAG. https://doi.org/10.1016/j.aeue.2020.153344

Chicago

Sahani, Jagdeep Kaur, Anil Singh, and Alpana Agarwal. 2020. “A Fast Locking and Low Jitter Hybrid ADPLL Architecture with Bang Bang PFD and PVT Calibrated Flash TDC.” AEU: International Journal of Electronics & Communications 124 (September): N.PAG. doi:10.1016/j.aeue.2020.153344.