A high speed BiCMOS comparator ASIC with voltage adjustable hysteresis.

A design of high-speed comparator ASIC, fabricated in 0. 35 μ m SiGe BiCMOS process is presented. This ASIC is designed as a part of the front-end readout electronics development for Resistive Plate Chamber detector of Iron Calorimeter experiment of India based Neutrino Observatory. The ASIC comprises eight channels of high-speed voltage comparator with LVDS driver. A novel technique is used to implement a small voltage adjustable hysteresis in the comparator without additional power, area and circuit complexity. This ASIC multiplexes input analog signals through an on-chip high-speed 50 Ω cable driver. The analog multiplexer supports daisy and non-daisy modes for access of input signals. The ASIC has power consumption of ∼ 13 mW/channel. The comparator LVDS output rise time is ∼ 900 ps. The measured timing precision of the ASIC is ∼ 40 ps RMS. [ABSTRACT FROM AUTHOR]