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A high speed BiCMOS comparator ASIC with voltage adjustable hysteresis.
- Source :
-
Nuclear Instruments & Methods in Physics Research Section A . Nov2020, Vol. 980, pN.PAG-N.PAG. 1p. - Publication Year :
- 2020
-
Abstract
- A design of high-speed comparator ASIC, fabricated in 0. 35 μ m SiGe BiCMOS process is presented. This ASIC is designed as a part of the front-end readout electronics development for Resistive Plate Chamber detector of Iron Calorimeter experiment of India based Neutrino Observatory. The ASIC comprises eight channels of high-speed voltage comparator with LVDS driver. A novel technique is used to implement a small voltage adjustable hysteresis in the comparator without additional power, area and circuit complexity. This ASIC multiplexes input analog signals through an on-chip high-speed 50 Ω cable driver. The analog multiplexer supports daisy and non-daisy modes for access of input signals. The ASIC has power consumption of ∼ 13 mW/channel. The comparator LVDS output rise time is ∼ 900 ps. The measured timing precision of the ASIC is ∼ 40 ps RMS. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 01689002
- Volume :
- 980
- Database :
- Academic Search Index
- Journal :
- Nuclear Instruments & Methods in Physics Research Section A
- Publication Type :
- Academic Journal
- Accession number :
- 146118534
- Full Text :
- https://doi.org/10.1016/j.nima.2020.164503