Cite
Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools.
MLA
Martins, Ricardo, et al. “Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-Nm CMOS Fully Supported by EDA Tools.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers, vol. 67, no. 11, Nov. 2020, pp. 3965–77. EBSCOhost, https://doi.org/10.1109/TCSI.2020.3009857.
APA
Martins, R., Lourenco, N., Horta, N., Zhong, S., Yin, J., Mak, P. I., & Martins, R. P. (2020). Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools. IEEE Transactions on Circuits & Systems. Part I: Regular Papers, 67(11), 3965–3977. https://doi.org/10.1109/TCSI.2020.3009857
Chicago
Martins, Ricardo, Nuno Lourenco, Nuno Horta, Shenke Zhong, Jun Yin, Pui In Mak, and Rui P. Martins. 2020. “Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-Nm CMOS Fully Supported by EDA Tools.” IEEE Transactions on Circuits & Systems. Part I: Regular Papers 67 (11): 3965–77. doi:10.1109/TCSI.2020.3009857.