Design and implementation of SFQ programmable clock generators

We have designed and implemented an SFQ programmable clock generator (PCG), which can generate the variable number of SFQ pulses according to its internal state. The PCG is composed of an SFQ ring oscillator, a control circuit which counts up the number of SFQ pulses and stops the operation of the ring oscillator, and a decoder which defines the initial state of the control circuit. The PCG can generate the variable number of SFQ pulses ranging from 2 to 2N, where <f>N</f> is the number of T flip-flops in the control circuit. The oscillation frequency of the PCG is designed to be ranging from 6.2 to 18.8 GHz. In this study, we have implemented a PCG generating SFQ pulses ranging from 2 to 24 using a cell-based design methodology and confirmed its correct functionality. [Copyright &y& Elsevier]