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Thermal Stress-Aware CMOS–SRAM Partitioning in Sequential 3-D Technology.
- Source :
-
IEEE Transactions on Electron Devices . Nov2020, Vol. 67 Issue 11, p4631-4635. 5p. - Publication Year :
- 2020
-
Abstract
- This article explores the feasibility of high-temperature annealing for top-tier devices in a sequential 3-D (Seq3D) technology. Thermally stable bottom-tier device and interconnect design guidelines are provided. CMOS–SRAM partitioning is proposed to achieve performance gain from Seq3-D. The implications of thermally stable Seq3-D on system-level performance are evaluated. Seq3-D wafer and die cost of ownership are estimated. [ABSTRACT FROM AUTHOR]
- Subjects :
- *RANDOM access memory
*TECHNOLOGY
Subjects
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 67
- Issue :
- 11
- Database :
- Academic Search Index
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- 147319715
- Full Text :
- https://doi.org/10.1109/TED.2020.3023923