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READ: A fixed restoring array based accuracy-configurable approximate divider for energy efficiency.

Authors :
Arya, Neelam
Soni, Teena
Pattanaik, Manisha
Sharma, G.K.
Source :
Integration: The VLSI Journal. Jan2021, Vol. 76, p1-12. 12p.
Publication Year :
2021

Abstract

Energy efficiency has emerged as one of the most essential design parameters in contemporary computing system design. Approximate computing is a new computing paradigm to achieve energy efficiency by trading-off energy/area/latency improvements with accuracy for error-resilient applications. This paper proposes R econfigurable E nergy-efficient A pproximate D ivider (READ) that achieves several energy–quality configurable modes using fixed restoring array divider architecture. Conventional approximate binary dividers require various divider hardware configurations to achieve distinct energy–quality trade-off points, which decreases the hardware flexibility, especially for modern embedded systems. READ accomplishes energy efficiency while meeting the dynamically varying accuracy requirements of the targeted application. READ uses reconfigurable subtractor cells that can work in either accurate or approximate mode using a subtractor cell controller logic. The paper also introduces the design of overflow detector using minimal hardware resources. A comprehensive accuracy and hardware evaluation on CMOS 45-nm technology node are performed for the proposed dividers as well as other state-of-the- art divider designs. Compared to the accurate 16 ∕ 8 divider design, the proposed divider shows an improvement of 49% in terms of energy efficiency and is 1.26x faster, while introducing minimal errors. The proposed divider design is demonstrated for its efficacy in image processing tasks and shows nominal effect on the output quality. • A fixed restoring array based approximate divider is proposed and presented with detailed error and circuit analysis for CMOS-45 nm technology node. • The approximate divider presented is reconfigurable in runtime which enables accuracy configurability by varying the design parameter. • Reconfigurable half and full subtractor cells are designed and proposed which achieves dual mode of operation — accurate and exact with energy savings. • Overflow detector circuit for divider design is proposed and presented which is scalable and hardware efficient. • The approximate divider designs are evaluated for image processing applications and found to be satisfactory in terms of Quality of Services (QoS). [ABSTRACT FROM AUTHOR]

Details

Language :
English
ISSN :
01679260
Volume :
76
Database :
Academic Search Index
Journal :
Integration: The VLSI Journal
Publication Type :
Academic Journal
Accession number :
147551795
Full Text :
https://doi.org/10.1016/j.vlsi.2020.08.002