Real-time automated register abstraction active power-aware electronic system level verification framework.

All modern low power system on a chip (SoC) architectures are equipped with an in-built power management system. Every new system is expected to have more features and lower power consumption, resulting in a continuous demand to improve energy efficiency. To cope up with the ever increasing demand, an active power-aware management verification architecture is necessary to minimize the power consumption. Power reduction techniques include clock-gating, power-gating, multi-voltage, and voltage-frequency scaling. The proposed verification architecture utilizes the Unified Power Format (UPF) 2.1 libraries to achieve early design verification at the Electronic System-Level (ESL) of abstraction. The proposed testbench can verify several designs of different power management schemes. The presented work offers a reduction in power states, CPU time and simulation time as compared to existing techniques. The interactive formal and simulation-based verification methods are used in this paper to remove the simulation artifacts during functional and power co-simulation. Additionally, this paper incorporates functional correctness and power-aware checks for different modules of Design Under Verification (DUV) at Transaction-Level Modeling (TLM). The proposed verification architecture supports active power management, TLM stimulus-based functional verification, automated register abstraction layer verification and automated coverage and power checks. The testbench architecture attains the following objectives of power-aware management and functional verification Intent: • Simulations of power-aware management unified power format (UPF) architecture using electronic system level (ESL) abstraction for early verification. Visualization of failure, isolation or retention. Automatic power checks for power management errors. • Addition of transaction-level modeling based stimulus generation in testbench for functional verification of design with assertion based self-checking mechanism. • Automated register abstraction layer implementation on testbench for register power-aware verification. • Collection of power states, transition coverage and functional coverage with automated coverage and power checks. • Implementation of real-time automation for valid scenario generation in minimum execution time. [ABSTRACT FROM AUTHOR]